1. Field of the Invention
The present invention relates to a method for manufacturing a bottom substrate of a liquid crystal display device and, more particularly, to a method for manufacturing a bottom substrate of a thin film transistor liquid crystal display device (TFT-LCD).
2. Description of Related Art
Compared with the conventional cathode ray tube monitor, the liquid crystal display device has the advantages of low power consumption, compact size, and non-radiation. However, the manufacturing of the liquid crystal display device is relatively complex and costly. In particular, the number of masks needed in the photolithography and etching processes can not be reduced effectively. As a result, the manufacturing cost of the thin film transistor array can not be further decreased yet.
In general, the manufacturing process of the thin film transistor array uses five masks to carry out the photolithography and etching processes and thus define the components of the thin film transistor array. With reference to FIGS. 1a to 1e, the first mask is used to pattern the first metal layer and then form the patterned first metal layer 32, which includes a gate electrode 321 of a thin film transistor, a bottom electrode 322 of an auxiliary capacitor, and the terminal pad 323. The second mask is used to define the semiconductor layer 36 and the ohmic contact layer 38 of the thin film transistor, as shown in FIG. 1b. 
Comparing the shape and position of the patterned first metal layer 32 in FIG. 1a and that of the semiconductor layer 36 and the ohmic contact layer 38, it is obvious that the pattern of the first mask is different from that of the second mask. This means the first photolithography and etching process and the second photolithography and etching process can not use the same mask.
Next, the third mask is used to pattern the second metal layer 40 and thus form the patterned second metal layer 40, as shown in FIG. 1c. The patterned second metal layer 40 comprises a source electrode 401 and a drain electrode 402 of the thin film transistor, and a top electrode 403 of the auxiliary capacitor. The fourth mask, as shown in FIG. 1d, is used to pattern the planar layer 44 and the passivation layer 42. Consequently, a contact of drain electrode 511 or a contact of terminal pad 512 is formed. It is possible to form the passivation layer 42 only, the planar layer 44 only, or both the passivation layer 42 and the planar layer 44. If both the passivation layer 42 and the planar layer 44 are formed, the sequence of the passivation layer 42 and the planar layer 44 is not limited. Next, as shown in FIG. 1e, the fifth mask is utilized to pattern the transparent conductive layer 46 and form the pixel electrode. As the shape and the position of the various components defined by the five photolithography and etching processes are different, it is necessary to use five masks for manufacturing the thin film transistor array.
However, the manufacturing cost of the mask becomes more and more expensive due to the increasing size of the thin film transistor liquid crystal display (TFT-LCD). Therefore, it is desirable to provide an improved method to mitigate and/or obviate the aforementioned problems.